Low-power 2D Gate-all-around Logics Via Epitaxial Monolithic 3D Integration

Innovations in device architectures and materials promote transistor miniaturization for improved performance, energy efficiency and integration density. At foreseeable ångström nodes, a gate-all-around (GAA) field-effect transistor based on two-dimensional (2D) semiconductors would provide excellent electrostatic gate controllability to achieve ultimate power scaling and performance delivering. However, a major roadblock lies in the scalable integration of 2D GAA heterostructures with atomically smooth and conformal interfaces. Here we report a wafer-scale multi-layer-stacked single-crystalline 2D GAA configuration achieved with low-temperature monolithic three-dimensional integration, in which high-mobility 2D semiconductor BiOSe was epitaxially integrated by high-κ layered native-oxide dielectric BiSeO with an atomically smooth interface, enabling a high electron mobility of 280 cm V s and a near-ideal subthreshold swing of 62 mV dec. The scaled 2D GAA field-effect transistor with 30 nm gate length exhibits an ultralow operation voltage of 0.5 V, a high on-state current exceeding 1 mA μm, an ultralow intrinsic delay of 1.9 ps and an energy-delay product of 1.84 × 10 Js μm. This work demonstrates a wafer-scale 2D-material-based GAA system with valid performance and power merits, holding promising prospects for beyond-silicon monolithic three-dimensional circuits.