Low Hysteresis Carbon Nanotube Transistors Constructed Via a General Dry-Laminating Encapsulation Method on Diverse Surfaces

Electrical hysteresis in carbon nanotube thin-film transistor (CNTTFT) due to surface adsorption of HO/O is a severe obstacle for practical applications. The conventional encapsulation methods based on vacuum-deposited inorganic materials or wet-coated organic materials have some limitations. In this work, we develop a general and highly efficient dry-laminating encapsulation method to reduce the hysteresis of CNTTFTs, which may simultaneously realize the construction and encapsulation of CNTTFT. Furthermore, by virtue of dry procedure and wide compatibility of PMMA, this method is suitable for the construction of CNTTFT on diverse surface including both inorganic and organic dielectric materials. Significantly, the dry-encapsulated CNTTFT exhibits very low or even negligible hysteresis with good repeatability and air stability, which is greatly superior to the nonencapsulated and wet-encapsulated CNTTFT with spin-coated PMMA. The dry-laminating encapsulation strategy, a kind of technological innovation, resolves a significant problem of CNTTFT and therefore will be promising in facile transferring and packaging the CNT films for high-performance optoelectronic devices.